It is well known to construct a memory array, such as a first-in first out (FIFO) buffer, having a variety of restrictive flags. Various restrictive flags include, but are not limited to, a full flag that limits the writing to the FIFO when the FIFO is full, an empty flag that limits the reading of the FIFO when the FIFO is empty, a half-full flag that indicates when the FIFO is half-full, an almost full flag that indicates when the FIFO is almost full, an almost empty flag that indicates when the FIFO is almost empty, and a write-read word line equality signal that indicates when the read and write pointers are equal. The various status flags prevent undesirable effects such as under-running the FIFO or over-running the FIFO. The various status flags provide indispensable information used during the implementation of the FIFO. However, the status flags can be an inhibiting factor when it is desirable to perform an advanced FIFO test. Various advanced FIFO tests include, but are not limited to, data retention testing, debugging array contents and monitoring the effect of the write word line being equal to the read word line without any bit-line shorters. With the various status flags present, it is impossible for the user to manipulate the read and write word lines arbitrarily (at will) throughout the FIFO array. The user is strictly held to legal operations to the FIFO array based on the actual status flags. For the user to perform advanced tests such as data retention, a complex repetition of writing to the FIFO until it is full and then reading from the FIFO until it is empty would have to be performed until all the memory cells are written to and read from. In a typical case where the FIFO depth is a fraction of the actual number of memory cells in the array, this repetition would have to be performed multiple times consuming vast amounts of test time. With the status flag restrictions in place, there is no way to read every memory cell in the memory core. Additionally, there is no way to write every memory cell in the memory core. The status flag inhibits under-running and over-running of the FIFO. An alternative would be to probe the internal silicon of the FIFO to determine the contents of the FIFO array. This is a difficult process and is not normally available at the packaged level of the FIFO.
The status flags inhibit the user from having complete control of the read and write pointers within the FIFO array. Additionally, the data retention testing time required with the status flags enabled can be very long. Therefore, it is impossible to write the memory core completely full and read the memory core completely empty, and it is correspondingly impossible to determine preferential states in the memory array after initial power-up or any particular sequence of events.
Referring to FIG. 1, a prior art FIFO buffer 10 is shown generally comprising a memory array 12, an input register block 14, an output register block 16, a write clock generator 18, a read clock generator 20 and a status flag logic block 22. The input register block 14 receives an input 23 from a data bus 24. The input register block 14 presents an output to a data bus 26 that is received by the memory array 12. The input register block 14 also receives an input 28 from an output 36 of the write clock generator 18. The input 28 represents a control signal that suspends the write pointer control 38 and the input register block 14 when a flag is received from the status flag logic block 22 indicating that the memory array 12 is full.
The write clock generator 18 receives an input 30 from an external write clock and an input 32 from the status flag logic block 22. The write clock generator 18 presents an output 36 that is received by a write pointer control 38 and the input 28 of the input register 14. An output 40 is received by the status flag logic block 22. When the status flag is received at the input 32, the write clock generator 18 sends a control signal over the output 36 that suspends the write pointer control 38, the input register 14 and ultimately the memory array 12.
The read clock generator 20 receives a first input 42 from an external read clock and a second input 43 from the status flag logic block 22. The read clock generator 20 has an output 44 that is presented to a read pointer control 46 and to the output register block 16. An output 50 is presented to the status flag logic block 22. The write pointer control 38 presents a series of inputs 52a and 52b thru 52i to the memory array 12. Similarly, the read pointer control 46 presents the number of outputs 54a and 54b thru 54i to the memory array 12. The status flag logic block 22 implements the various status flags that restrict the input received by the memory array 12 through the data bus 26. The status flags also restrict the information received by the output register 16 from the memory array 12. The status flags make it impractical to test the entire contents of the memory array 12 during post production quality control or impossible during other advanced testing routines.